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Semis Memo: Supply Chain Inheritance Power & Analog Semis, CPUs in the Agentic Era, Neoclouds, Material Bottlenecks, Korea Unlocked CITRINI MAY 12, 2026 ∙ PAID For the first innings of the AI Infrastructure trade, it was simple enough just to know the basics. Large Language Models run on GPUs, buy Nvidia. AI compute will lift optics out of the telecom doghouse and cause significant growth for interconnects, buy the optical interconnect names. Every iota of AI compute demand in the agentic era must inevitably flow through the memory OEMs, buy Micron and SK Hynix. It seemed a lot more difficult than that at the time, but it was pretty much that simple.

The reasons for that were twofold. First, not everyone bought into the massive growth in data centers that would be required for AI to proliferate and actualize. Second, between the post-COVID supply chain glut and numerous other headwinds to semiconductor and adjacent names, valuations remained quite forgiving in all but the most obvious first-order beneficiaries. That’s begun to change, and with it, outperforming in the AI infrastructure complex requires in-depth understanding beyond just identifying current bottlenecks. Understanding the roadmap for the future requires a bit more technical competence, which is why in January 2026 we began our Semis Memo series – guided by our semis analysts Zephyr and Jukan.

While the landscape has evolved, our framework stays the same. Begin with the macro. Find areas where forecasts are still reflecting overhangs from non-AI related Introduction headwinds and determine whether AI demand can overcome them in a way that makes estimates too low. In this issue, we’re covering the following places that meet our criteria: ● Analog and Power Semis: Supply Chain Inheritance ● CPUs in the Agentic Era ● Neoclouds: The Inference Shortage ● AI Materials Bottlenecks ● Korea Unlocked ● Updating Previous Semis Memo Ideas We end with Some Thoughts on Where We’re Going… We first flagged the likelihood that AI demand would overwhelm the headwinds currently being experienced by the analog and power semi sector in our 25 Trades for 2025, specifically as it related to the upcoming Multilayer Ceramic Capacitors (MLCC) shortage.

Components integral to power quality management systems address common issues such as voltage sags, harmonics, and transients, thereby ensuring the reliable operation of electrical and electronic equipment. This includes capacitors, inductors, diodes, power ICs, surge protectors, filters, transformers, uninterruptible power supplies (UPS). Discrete power semiconductors (like MOSFETs and diodes) will also benefit as they are integral to creating efficient, stable power rails. Filters, ferrite beads, and connectors may see growth, but the clearest secular uplift is likely in Analog and Power Semis capacitors and inductors given their centrality to power conversion in AI-driven, high performance computing environments.

These names have begun to outperform, and we feel it’s directly related to another framework we’ve posed for 2026 – “Post-Traumatic Supply Disorder”. The companies dealing with power semis have had to contend with a barrage of headwinds – the COVID supply glut, competition from Chinese analog semis, the anemic EV and automotive cycle…the list goes on. However, they’re beginning to see data center revenues climb. And they’re not rushing to add capacity, having been burnt one too many times. Take a look at the capex intensity (capex / revenue) for Texas Instruments (TXN US): It’s typically this part of the cycle that results in supply ramping, but instead, TXN and peers like NXP Semiconductors (NXPI US) are content to raise prices.

Now, we’re at an inflection point, and these companies are letting ASPs go up rather than flood the market. Up until now, however, we’ve been mostly focused on the rack-internal story. Companies like Murata Manufacturing (6981 JP), Vishay Intertechnology (VSH US) and Samsung Electro-Mechanics (009150 KS) have taken off as the crowd recognizes exactly how short on MLCCs we are. For our first and highest-conviction section, we’re glad to say that you don’t have to be a semiconductor expert to understand the rack-external power semis story. It’s a pretty cut and dry setup. The capex that burned them once was actually the exact infrastructure necessary for this part of the cycle.

While we’ve long been waiting for the automotive overhang to lift the fog off of the names in the analog and power semis space, we’re now realizing something more significant. It doesn’t really need to – rather, the AI capex buildout is simply inheriting the EV buildout supply chain. In Nvidia’s May 2025 technical blog on 800V DC rack architecture, they credit the underlying technology to “the electric vehicle and solar ” That’s the trade… Supply Chain Inheritance The most consequential power architecture transition in the history of computing is happening because Porsche, BYD, and a handful of solar inverter companies spent the last decade scaling a supply chain for completely unrelated end markets.

Nvidia inherited both the silicon and a half-decade of cost-curve compounding – walking into an automotive-validated, fully ramped wide-bandgap semiconductor industry. We’ve spoken about this before (in our 2025 Robotics Update), but it seems that the market is becoming increasingly aware of it now. Anyone who spent 2025 dumping SiC names on soft European EV demand is about to find out those names have a second customer cohort showing up at exactly the moment the first one is wobbling. Now, companies that spent the last 5 years in the doldrums of the EV and COVID supply glut aftermath find themselves with a massive moat made up of the capex they’ve spent (some of whom, the capex that bankrupted them!

More on that later). This supply chain inheritance is a result of AI capex becoming the apex predator of the global economy, sucking capital and capacity out of every adjacent industry. Here, AI sits on the receiving end of capacity that was built for someone else, with no requirement that the original industry stay healthy for the trade to work. (Indeed, the trade works better if the original industry is currently struggling, because the names are already mispriced on the original cohort’s weakness.) The Porsche engineers who specified the Taycan’s 800V powertrain in 2017 had no idea they were laying the foundation for a 600kW GPU rack in 2027.

They were, though. This is the next layer of the AI Power Plumbing thesis we’ve been building all year. The MLCC and discrete power semi work was the rack-internal story. The Inheritance is the rack-external story. The architecture itself is simpler than Nvidia’s engineering blog makes it look. (As always with Nvidia, the technical post goes hard on the physics, but the trade implications are direct.) Voltage doubles from the legacy 54V rack standard to 800V, which cuts copper requirements substantially and, more importantly, is the only path to physically building 600kW racks. The conversion stages from utility power down to the chip need wide-bandgap silicon at every step: silicon carbide (SiC) for the front-end down-conversion to 800V DC, gallium nitride (GaN) for the high-frequency step down to the intermediate voltages feeding the GPU.

Both have been in volume production for half a decade because of industries (EVs, fast-charging, solar inverters) that have nothing to do with AI. Do you know what it looks like when a stock goes from “beta to anemic EV/solar industry plagued by Chinese oversupply” to “critical supplier of the components necessary to jump over the power hurdle”? Neither do I, but this is probably closer to the start of it than the end. Today, eight power shelves per GB200 NVL72 sit inside the rack doing the conversion. At megawatt-class density those shelves would eat the entire rack, leaving zero room for compute.

In the new architecture, conversion moves upstream to a dedicated power shelf (sometimes called a sidecar), the IT rack receives DC directly. The picture below shows the bill-of-materials reweighting at the rack level. Total power BOM grows roughly 16% on the architecture transition (which is itself a tailwind for the supply chain in aggregate), but the mix shift is the actual story. Wide- bandgap silicon plus high-voltage connectors goes from zero percent of rack power BOM to roughly 64%. The chart below shows global silicon carbide demand by end market from 2018 through our 2030 estimate.

The EV cohort drove SiC from a $300 million industrial niche in 2018 to a $3.5 billion market by 2024, a roughly 12x expansion in six years. That growth has been decelerating into a plateau as European EV demand softens and Chinese capacity takes share. But AI infrastructure shows up as a meaningful demand layer for these names this year, with the first Rubin platform deployments at 800V, then steepens dramatically through 2028-2030 as Rubin Ultra ramps and hyperscalers commit to 800V DC for greenfield buildouts. By 2030, AI infrastructure is estimated to reach half of total SiC demand.

The wafers, importantly, are the same wafers. STMicroelectronics (STM US), ONSemi (ON US), Infineon (IFX GR),, went from having an EV problem to suddenly having free capacity at the exact time it was needed. What makes the trade asymmetric is that the SiC names are still being valued on the EV cohort. Take a look at Axcelis Technologies (ACLS US). The next twelve months of Nvidia design wins, hyperscaler architecture commitments, and supplier earnings commentary will reveal the second cohort to the market. Most colocation facilities operating today were designed for an era when 10 to 30 kW per rack was a stretch goal.

The chart below puts that legacy capacity next to where Nvidia’s roadmap is going. Read the x-axis carefully: it’s a log scale, because the bars wouldn’t fit on a linear one. A facility that was built to support 15kW per rack cannot be incrementally upgraded to support 600kW. The medium-voltage feed, the switchgear, the busways, the cooling infrastructure, the floor loading, the structural envelope itself in some cases are all wrong. In most cases, the only viable path forward is a full power infrastructure rebuild from the medium-voltage transformer inward, which is a different question from “is my colo provider

” It’s a question of whether the building can take the deployment at all. The large-scale operators – Digital Realty, Equinix, plus the private giants like Aligned and Compass – should have the capital and the greenfield pipelines to build for the new spec. If 800V DC distribution starts at the boundary of the data hall, something has to convert utility-grade medium-voltage AC into that 800V DC stream. Today that something is an iron-core transformer plus rectifier, a piece of equipment whose underlying technology has not meaningfully changed in a century, whose lead time is 18 to 30 months, and whose weight is measured in tens of tons.

The data center industry has run out of patience for iron-core transformers. Lead times have gone from “long” to ” Major hyperscaler builds are now bottlenecked on transformer delivery rather than land, power, or chips. The Upstream: The Solid-State Transformer Inflection replacement technology has been quietly maturing in parallel: Solid-state transformers (SSTs) are built on the same wide-bandgap semiconductor foundation as the rest of the 800V architecture. An SST is a power electronics device, not a passive electromagnetic one. It uses high-frequency SiC switching to convert medium-voltage AC directly to 800V DC in a single integrated unit, eliminating the legacy transformer plus AC-DC rectifier pair entirely.

The advantages compound across every relevant dimension: lead time (months rather than years), weight (a fraction of iron-core), physical footprint (similar reduction), functionality (built-in regulation, fault protection, bidirectional power flow), and electrical alignment with what 800V data centers actually want (native DC output). The SST opportunity falls mainly within the public companies that we’ve been discussing as part of the bipartisan, decades long fiscal push to modernize the grid – Eaton, ABB, Siemens etc. Three points matter: 1. Traditional transformer incumbents are positioning aggressively. ABB, Eaton, Schneider, Siemens, Hitachi Energy, and GE Vernova all have publicly announced SST programs or have made acquisitions.

These names are racing to get production- ready SST products to market for the 2027 deployment window and none of them have a winner-take-all position yet. 2. Pure plays still live in the venture world. In February 2026, Heron Power (founded by Drew Baglino, ex-Tesla SVP of Powertrain and Energy) closed a $140 million Series B led by a16z’s American Dynamism Fund and Breakthrough Energy Ventures, with plans to build a 40GW manufacturing facility. They claim 50GW of customer orders are already lined up. DG Matrix raised a $60 million Series A in the same window with ABB and Mitsubishi Heavy Industries participating.

Eaton acquired Resilient Power last year in a deal worth up to $150 million. Unfortunately for us, there haven’t been any pure-play SST IPOs. 3. SSTs widen the addressable market beyond AI capex. The same equipment that converts utility AC to 800V DC inside a hyperscale build is the equipment utilities need to modernize substations, integrate distributed renewable generation, and manage bidirectional EV charging loads. The customer base is materially bigger than the data center alone. That makes the SST piece of the basket less levered to AI capex digestion than the rest of the trade, which matters for downside protection.

Voltage regulator modules (VRMs) are the downstream story. They sit on the motherboard immediately adjacent to the GPU, taking the intermediate bus voltage (50V, 12V, or 6V depending on architecture) and stepping it down to the sub-1V core voltage that the silicon actually uses. The math of GPU power delivery has gone genuinely strange. A Rubin Ultra GPU is projected to draw upward of 2,500W. At a 0.7V core voltage, the VRM has to push roughly 3,500 amps into the silicon — not across transmission lines or factory busbars, but across a power plane the size of a paperback book.

Downstream: VRMs and the Thousand-Amp Problem GPU TDP evolution and the implied current draw at the silicon. The thousand-amp problem is a five-year-old problem; the three-thousand-amp problem starts in 2027. There is no single component that can handle that current density. The architectural response is multi-phase power delivery: dozens of parallel VRM channels each handling a fraction of the total load, synchronized in time to deliver clean current to the silicon. Phase counts have been exploding generation over generation, having quadrupled over the five years from H100 to Rubin Ultra, and each phase requires a controller IC, a high-side MOSFET, a low-side MOSFET (often integrated as DrMOS), inductors, and passive components.

Multiply phase count growth by the GPU volume curve and the VRM content per AI server is growing faster than almost any other category of semiconductor demand. Nvidia shipped roughly 4 million H100-class units in 2024 and is on track to ship 8- 10 million Blackwell-class units in 2026. Each generation roughly doubles the units shipped and roughly doubles the VRM content per unit. VRMs are also where the 800V transition matters most for downstream supplier share. In the legacy 54V architecture, VRMs perform a single step-down from 54V to ~1V. In the new 800V architecture, the intermediate bus voltage drops further (to 6V- 12V depending on topology), which makes the per-phase step ratio slightly easier, but the total power being delivered is higher, so phase counts keep climbing.

Net effect: more content per GPU, with share captured by whoever has the best efficiency, fastest transient response, and smallest physical footprint. Three names dominate the AI VRM market today. Monolithic Power Systems (MPWR US) is the incumbent supplier to Nvidia’s reference designs and has been the cleanest pure-play AI VRM expression for two years running. Vicor (VICR US) has been pushing factorized power architecture and vertical power delivery as alternative topologies, with mixed historical traction but growing relevance as power densities cross thresholds where conventional topologies hit physical limits. Renesas (6723 JP), via the Transphorm acquisition, is moving into GaN-based VRM topologies that offer better transient response at high phase counts.

The discrete power semis (ROHM, AOSL) capture content on the MOSFET side, but have higher risk still from EVs. In order to capture this admittedly wide universe, we’ve split the opportunities into four tiers of the value chain, mapping closely to Nvidia’s own 29-member 800VDC supplier alliance (announced at COMPUTEX 2025 and expanded through the October 2025 OCP Global Summit). Our conviction in the asymmetry descends by tier - most in Tier 3 and 4 have already re-rated and never had much of the EV overhang to begin with. Most of the names in Tier 1 still have yet to come close to their peak valuations from EV-mania.

Each tier captures a different slice of the share shift, and each carries a different conviction. Tier 1 (50% weight): Wide-bandgap silicon. Pure-play SiC and GaN producers, plus the capital equipment vendors who sell into them. Tier 2 (25% weight): Broad-line power semi & analog. Diversified semiconductor companies with SiC, GaN, and silicon power exposure, plus the VRM specialists driving the thousand-amp problem on motherboards. Tier 3 (15% weight): Power system components. The PSU, module, busbar, and interconnect ecosystem. Tier 4 (10% weight): Data center power systems and medium-voltage infrastructure. Sidecar power shelves, medium-voltage switchgear, transformers, and the SST programs that will replace iron-core transformers at the data center boundary.

This is the most consensus-discovered slice of the trade, but the content shift is real and the multiples can still expand. The Basket AI Rack Architecture · Wide-Bandgap, VRM & Power Infrastructure Basket md) md) md) md) You can find the basket on Citrindex here. And before you scoff at buying a chart that’s going vertical (although if that’s your default, you’re probably already having a pretty bad time), take a look at some of the most consequential names for 800V when zoomed out versus our 125-name Core AI Data Center Infrastructure basket. The market might be coming around to the realization of the supply chain inheritance, but it’s far from having repriced these as “AI names”.

Most AI infrastructure trades require the AI buildout to keep going, full stop. The supply chain inheritance trade has a second leg of demand under it (EVs, robotics, grid buildout, and industrial power) that makes it structurally insulated in a way that pure-play AI infrastructure trades aren’t. We are just now beginning to see the market reprice them as if EVs aren’t the only thing the wafers are doing. This memo is going to be long as-is, so I will simply refer readers interested in understanding the other kicker here (upside to the power needs for embodied AI / robotics) to our Humanoid Robots primer and Robotics Update article.

That second wave of demand that will hit over the coming years in addition to data centers will make this one of the hottest semi subsectors. There’s a particular type of setup we’ve been very fond of for the past two years: it’s the setup that we saw with our Crouching Tigers, Hidden Dragons in 2024-2025. It goes like this: Single-Stock Highlight: Wolfspeed (WOLF US) This was our idea behind names like Carvana (CVNA US), Sea Limited (SE US), and AppLovin (APP US) heading into 2025 and now it’s spilled over into the semis space.

Wolfspeed is the platonic ideal – not only did they spend aggressively to ramp capacity into demand that failed to materialize, they did it so hard that it bankrupted their company. Wolfspeed spent $6.5 billion building out its global SiC capacity, anchored by the world’s first 200mm SiC fab at Mohawk Valley and the John Palmour Manufacturing Center in Siler City, NC. Their bet was that EV adoption would absorb the capacity on schedule. EV adoption… didn’t absorb the capacity on schedule. The stock, originally CREE, went from $140 to single digits and filed Chapter 11 in June 2025.

Bondholders took control in a debt-for-equity swap that wiped out the old holders. Sorry, previous WOLF equity holders. Now, however… The setup now, on the other side of bankruptcy, is perfect. The infrastructure is coveted – Mohawk Valley is still the only 200mm SiC fab operating at commercial scale in the entire world. The John Palmour facility is the largest SiC wafer fab ever built. The physical capacity that took five years to build now finds itself in a place where the EV cohort doesn’t really matter anymore, and the AI infrastructure cohort needs their capacity to get to the next level.

And, as we all know, nothing gets in the way of this train. The CREEdence Clearwater Revival The spending cycle that bankrupted them gives the restructured company an irreplaceable position in the physical supply chain that we just spent 10 pages outlining. The capex looked (and was) value destructive in 2023. By 2027, it will look like one of the most prescient infrastructure bets in the wide-bandgap industry. The market is beginning to price this as a turnaround – we think it should be priced as an unavoidable beneficiary. That’s our base case, right now.

WOLF is a crouching tiger getting ready to reveal a dragon that deserves to not just be priced based on what their fab’s replacement value theoretically is, but reflect the fact that it’s not going to be replaced. By anyone. They’re the only game in town. But wait, there’s more. Beyond getting paid as AI infrastructure absorbs that 200mm capacity, there’s the 300mm kicker where either WOLF will repeat the exact same mistakes (which would be kind of funny) or cement its lead for decades to come. First, a disclaimer: there are no 300mm Silicon Carbide wafer production or fabrication facilities online anywhere in the world.

Market consensus sees this as a 6- 8 year roadmap with more clear risks than reward, we just saw $10 billion of capital destruction for a single 200mm buildout, so why the optimism here? Why now? Because the same property that made SiC useful at the edges of a data center (absurd thermal conductivity) makes it a candidate to receive an invitation much closer to the silicon itself. As we have said repeatedly in our coverage of the upstream to downstream AI material bottlenecks - The closer a material sits to the chip, the more pricing leverage its vendor has over the customer.

At the periphery, SiC competes on price like any other power material. Inside the package, the economics flip entirely. The catalyst here is thermal. Modern AI packages are pushing 1,000W+ through a footprint smaller than a credit card, and current cold-plates (copper or aluminum, sitting on top of a thermal interface material on top of the die) are a tower of bottlenecks. SiC has roughly 3x the thermal conductivity of copper once you account for metallization stack penalties, and dropping a SiC cold-plate directly onto the back of a die assembly improves the heat path dramatically.

The natural extension is to machine fluid cooling channels directly into the SiC substrate itself, which is the active cooling concept that NASA was funding a private American company called Eotron to demonstrate over a decade ago. Eotron is still doing that work today. The proposed “Silicon Cold Plate” sits in direct contact with high thermal flux devices and removes waste heat through internal fluid channels, while also routing electrical and system connections through the same substrate. Take this one step further and chiplet interposers themselves get fabbed from SiC, with through-vias and communication fabrics carved directly into a substrate whose backside is doing the thermal work.

We know the science is real. We know the demand will be enormous. So why hasn’t anyone built this yet? Geometry. Straight up sixth grade geometry. If you missed our discussion about the importance of advanced packaging in 26 Trades for 2026, well, sorry, you could have made some serious money if you hadn’t, but we’ll refresh quickly. Modern AI accelerators have outgrown the reticle (the hard physical cap on the size of a single die, roughly 850mm² for EUV). Once you exceed that limit, you have to use chiplets (a bunch of smaller chips packaged together), which means you need a substrate or interposer big enough to host multiple chiplets next to each other.

The AMD MI300A package lands around 75x72mm. Blackwell GPU packages are roughly 70x76mm. We are not done climbing. Jensen Huang holds a Grace CPU (your left), a Blackwell GPU die (center), and a fab tech holds an extra-large AMD package (your right, not to scale) The extreme case is Cerebras, which skipped chipleting altogether and claimed an entire wafer as one die. As if a boomer product manager showed up one day and said “what if we just made one big ” and the engineers said “no you can’t do…well, I mean, okay yeah technically that could work”.

But notice anything about these chips when compared to wafers (which you’ll recognize the shape of from TSMC logo fame). A wafer is a round disk. The chips you want to cut out of it are squares. That’s a problem, because you can’t start your square at the edge of a circular wafer (you need clean straight edges so the squares can be stacked, bonded, or grown vertically into other dies without defects propagating from a curved boundary). Wafers already throw off a lot of wasted material, this would take that to the extreme even before accounting for the impact a single defect could have.

Bump the diameter up by 50% to 300mm and suddenly you fit four of those packages on the same wafer. The math moves from “wildly uneconomic” to “viable jpeg) Read-through md) Simplified model: It does not account for wafer notch, real die-placement optimization, defect traps, looswarp, wafer thickness, process exclusion cones, metallization/bed coupons, component shape variants, or yield-learning jpeg) The obvious next question: is Wolfspeed working on this, and did the relevant assets survive the bankruptcy? Yes, and yes. In January 2026, the post-restructuring company demonstrated production of a single 300mm SiC crystal. Yes, it’s only one wafer.

But Wolfspeed is one of only two companies on earth that has shown this capability (Coherent is the other), and Wolfspeed is the only one of those two whose entire business identity is wide-bandgap materials. Coherent has SiC as a division. Wolfspeed is SiC. Current equity holders are free-and-clear of the debt overhang from the previous (EV focused) build-out and are primed to ride the coattails of larger-die AI accelerators to the heart of the data center rather than just the periphery. If the story were just about EVs, 300mm SiC wafers are probably an early-2030s reality, but the massive margins and urgent aggression of frontier AI companies could easily pull this forward to reality before the 2020s wind down.

The cherry on top is that New York State has ‘invested’ billions of dollars off of the balance sheet and does not expect direct repayment, so the deck is stacked in our favor on this one. The MTA alone needs to replace 190 4MW “power traction” substations just for the NYC subway while 300+ miles of track on LIRR/MNR are being electrified as well as a healthy rolling stock cycle. Then you have city and school buses going zero emission by 2030 and the charging infrastructure required for that. Oh, and let us leave you with one more hook: Elon Musk will need a metric ton of these components and has a vested interest in promoting American manufacturing.

As we covered in Agentic Utilities – the next phase of AI is about models that can do things. A chatbot answers a prompt or query. An agent completes a task. It searches, plans, retrieves, calls APIs, runs code, checks results, updates memory, coordinates with other agents, and then calls the model again. The model is still essential, but it is no longer the whole workload. The workload has transformed into a loop and that loop needs orchestration. Conveniently, this is where the CPU comes back into the AI story. GPUs generate tokens; CPUs keep the agents moving.

Agents tend to use 10-30x more tokens than chatbot interfaces. In the chatbot era, the user mostly experienced model latency. In the agentic era, the user now experiences workflow latency. The workload now involves an agent gathering context, calling tools, checking outputs, completing actions, and returning something useful to the user. That surrounding layer is where the CPU lives. CPUs in the Agentic Era As we laid out in Interconnects 101, a CPU isn’t equipped to do the dense matrix math that makes GPUs optimal for training and inference. The CPU acts as the general-purpose coordinator.

It is responsible for scheduling jobs, managing memory, handling the operating-system work, routing requests, and running the application logic. It coordinates storage, networking, security, virtualization, and I/O. It tells the accelerators (GPU/ASIC) what to do, sends them data, receives their outputs, and manages/monitors the whole process. In a normal chatbot interaction, that surrounding work is secondary, but in an agentic workflow, it becomes central. For example, in a coding agent, the GPU generates the code, but the CPU runs the shell, opens files, executes tests, reads logs, manages the repository, handles Python or Bash, and decides what should be sent back to the model.

For a research agent, the GPU may summarize and produce the output, but the CPU manages retrieval, search, ranking, document parsing, browser interaction, and API calls. In an enterprise agent, the GPU may reason, but the CPU handles permissions, databases, workflow systems, CRM updates, audit logs, and policy checks. Reinforcement learning environments bolster the CPU thesis. When AI systems are trained or evaluated through reinforcement learning, the GPU handles the dense matrix multiplication math, but the CPU often runs the environment that produces the next reward signal. This matters because RL is a repeated loop of action, environment step, and feedback.

Depending on the task being RLed, the environment for that task may involve physics simulation, rule-based logic, API calls, database queries, sandboxed code execution, unit tests, web navigation, or multi-agent interaction. These environment steps are difficult to parallelize cleanly on GPUs. As a result, large-scale RL can become constrained by how quickly CPUs can generate experience/data for the model to learn from. The more the industry uses RL to make agents reliable, autonomous, and task-oriented, the more demand rises for the high- core-count CPUs, memory bandwidth, fast storage, and low-latency networking needed to keep GPUs fed with useful training and evaluation data.

Nvidia is building Vera as they want to own the AI factory. Arm Holdings (ARM US) is building AGI CPU as they want to expand from IP into datacenter silicon. Intel is defending the host CPU layer in Nvidia systems, as they want to preserve the x86 host layer. AMD (AMD US) is pairing EPYC and Instinct while trying to sell balanced infrastructure. Qualcomm’s (QCOM US) Snapdragon suite is jockeying to win the on-device orchestration layer within agentic workflows, with the X2 Elite Extreme outperforming benchmarks for multi-threaded productivity tasks. Amazon, Google, and Microsoft want custom silicon control and less dependence on the silicon designers.

Each company is taking a different approach, but the direction is the same: the workload is becoming more heterogeneous, and the CPU is becoming more strategic. The scarce resource moves from just FLOPS to useful work per rack, per watt, per dollar, and per second. That means the control/orchestration plane becomes investable. The control plane includes high-core-count CPUs, coherent CPU-GPU interconnects, PCIe and CXL, memory-rich servers, fast storage, low-latency networking, DPUs, secure sandboxes, inference runtimes, orchestration software, vector databases, and observability. Connectivity silicon and design IP that enable host-to-device orchestration, PCIe switching, CXL fabrics, and data movement.

md) Programmable network adapters that offload packet processing, virtualization, security, and infrastructure functions from CPUs. md) High-speed switching, interconnect, and link-enabling components for low-latency AI and cloud networks. md) Citrini Research In the first AI trade, investors mostly cared about the accelerator supplier. In the agentic trade, they should care about how much actual work a system can complete end-to-end. There is also a strategic observation here: agents make AI less like a calculator and more like an operating system. Once AI systems are continuously acting, the model becomes one component in a larger control loop.

The control loop needs general- purpose compute. It needs to branch, wait, retry, authenticate, serialize, sandbox, fetch, compress, search, and coordinate. The bear case is that some of today’s CPU bottlenecks are software artifacts. The latency stems from Python overhead, poor batching, weak serialization, and immature schedulers, which can be improved. That is true, but the fix for expensive GPU underutilization is better CPU-side scheduling, faster tokenization, cleaner data movement, and more efficient orchestration, then the leverage still exists at the CPU/control plane level. The bottleneck can migrate from hardware to software, but it still remains outside the raw GPU matrix math.

Our focus shouldn’t simply be on Intel, AMD, and Arm. All three will benefit (and are benefitting) from the agentic AI cycle, but this has already been reflected in their stock price. Before all of you look at the image above and go “yeah, we know” – what the market has just now begun to reprice is the orchestration plane, and this is the primary jpeg) Source: Citrini Research as of 2026-05-11 at market close Positions in basket md) You can view the basket on Citrindex here. Here are some specific single stocks to highlight...

ASPEED (5274 TT) ASPEED is a fabless chip designer known for their BMC (baseboard management controller) chips. A BMC chip is present on a server or rack module that lets operators monitor, control, secure, update, and troubleshoot the system independently of the host CPU/GPU operating system. ASPEED has 80% market share for BMC chips in general CPU servers. They also have 100% market share in BMCs for Nvidia’s Hopper/Blackwell servers. Each Blackwell NVL72 has 87 BMC chips, and BMC chip content is expected to grow with the next generation Rubin servers. Liquid cooling is a great driver for ASPEED.

Liquid cooling systems embed many liquid detection sensors, requiring BMCs to instantly issue precise power-off commands upon detecting minute amounts of moisture within milliseconds. ASPEED has an ASML-like moat in BMCs. Just like every leading-edge chip is fabbed using ASML’s EUV tool, ASPEED’s BMC chips are present in x86 CPU servers, Arm-based CPU servers, RISC-V CPU servers, Nvidia GPU racks, AMD GPU racks, Trainium or TPU racks. ASPEED initially forecast BMC TAM at around 46.5 million chips by 2030, but due to growing demand for AI servers and agentic AI, they revised the TAM to 65 million chips by 2030, with BMCs used in AI servers growing 40% in 2027, 35% in 2028, and 30% in 2029–2030.

We are seeing volume growth at the same time that the ASP of BMC chips is rising as more security and control functions are integrated into them. We can already see the growth from agentic AI demand in their financials. Management had guided Q1 2026 revenue to NT$2.6–2.7 billion with a gross margin of 66.5–67.5% in November 2025. However, the actual Q1 2026 revenue is about NT$3.14 billion, based on the monthly revenue data, which has exceeded that original revenue outlook by roughly 17–21%. LOTES (3533 TT) LOTES is a precision connector, CPU sockets, memory connectors, high-speed interconnects, cable assemblies and liquid-cooling hardware manufacturer.

They emphasize their vertically integrated production model with in-house design, tooling, molding, stamping, electroplating, and automated assembly. The biggest upside for LOTES comes from their CPU socket sales for Intel, AMD, and Arm platforms, as well as memory connectors, including DDR, SO-DDR and CAMM and Quick Disconnects (QD) for liquid cooling. LOTES has around 35% global market share in CPU sockets. A key underappreciated driver is not only more CPUs, but more valuable CPU sockets. As next-generation server CPUs increase in pin count, socket complexity, and ASP should rise. Recent company commentary indicated that 2026 CPU sockets average roughly 5,000 pins, with next-generation platforms expected to exceed 7,000 pins.

This creates a content-per-server tailwind even before factoring in unit growth. At its March 2026 investor meeting, LOTES indicated that 2026 revenue could grow about 15%, with the server business up about 30%, continuing last year’s strong server momentum. LOTES reported that Q1 2026 revenue reached NT$9.38 billion, up 21% year over year. This compares favorably with management’s full-year revenue growth target of roughly 15%, suggesting that guidance could prove conservative if server momentum continues into the second half. We believe that they will beat that target and revenue growth will accelerate, especially by Q3/Q4.

The product mix is also shifting more towards servers, away from consumer products, which will be favorable for their growth. Because of raw material costs, especially due to higher copper, gold, and resin prices, the company has started negotiating price increases with its customers. This is a big break from the past, as LOTES used to make small price cuts every quarter for their customers. Management also stated that server order visibility had improved from 4-6 weeks last year to 12 weeks to 4 months. LOTES is also expanding outside China, which may become increasingly important for hyperscale and server customers seeking supply- chain diversification.

Factories in Vietnam were responsible for 16% of revenue in 2025, with the management targeting 20%-25% this year. More than 70% of Vietnam’s capacity is focused on server products. This gives LOTES a strategic advantage if customers require non-China capacity for AI-server supply chains. FIT Hon Teng (6088 HK) Foxconn Interconnect Technology, or FIT Hon Teng (6088 HK), is the interconnect and precision-component arm of the Hon Hai/Foxconn group. Like LOTES, FIT supplies CPU sockets, memory sockets, DDR5 DIMM connectors, PCIe CEM connectors, M-CRPS power connectors, high-speed internal cables, and backplane products. FIT has 40% market share in CPU sockets.

The upside for FIT comes from their CPU socket sales, high-speed 224G+/448G connectivity, optical interconnects, cabinet connectors, and high-speed cables. FIT’s long-term guidance shows Cloud/Data Center revenue mix rising from 16% in 2025 to the mid-20% range in 2026, high-20% range in 2027, and low-30% range by 2028. We expect them to easily beat this forecast. Montage Technology is a fabless semiconductor design company focused on high- speed interconnect chips for cloud computing and AI infrastructure. They primarily design and sell memory-interface chips, PCIe/CXL interconnect chips, CXL memory expansion controllers, and clock chips. The company is positioning itself as a “content per server” beneficiary since higher demand for agentic AI workloads Montage Technology (6809 HK)

requires more CPU servers, more memory capacity and higher memory bandwidth, demand rises for DDR5 server modules and the interface chips used on those modules. The first growth driver for Montage is higher DDR5 content per server. Every CPU server requires memory modules, and Agentic AI requires more host memory alongside the XPU’s HBM. Montage benefits because they design RCD, DB, MRCD/MDB, PMIC, which are present on server memory modules and help CPUs access memory faster in a more reliable manner. The second driver is rising silicon content per module. As CPU core counts and memory speeds increase, signal- integrity challenges become harder, increasing the importance of interface chips.

This is especially relevant for newer high-bandwidth memory-module architectures such as MRDIMM/MCRDIMM, where Montage sells MRCD and MDB chipsets in addition to conventional DDR5 interface products. The third growth driver is PCIe/CXL connectivity. AI servers require high speed links between CPUs, GPUs, accelerators, SSDs and NICs. Montage’s PCIe Retimers compensate for channel attenuation, reduce jitter, and extend high-speed signal reach in servers, storage systems, and accelerators. Its CXL MXC chips provide another growth vector by enabling memory expansion, pooling and sharing across hosts, which can improve memory utilization in data-intensive AI workloads. Montage was the largest supplier of memory interconnect chips in 2024 and held a 36.8% market share.

Q1 2026 was exceptionally strong for Montage, gross margin reached 69.8%, up 9.3% YoY, driven by strong shipments of DDR5 RCD chips and new interconnect products. Interconnect-chip gross margin reached 71.5%, up 7.0% YoY. Gross profit reached RMB1.019 billion, up 38.0%. Our pet favorite for 2026 has been Qualcomm, and it has certainly tested our patience. The stock was a let-down for the beginning of the year, trapped in a narrative treating it as a mature handset company with Chinese headwinds and fading licensing revenues. Now, however, the market is beginning to see a company that represents a truly asymmetric bet.

One of the cheapest names in the semiconductor index is now positioned to re-rate aggressively as a potential CPU winner with an on- device kicker. Qualcomm (QCOM US) The bull case rests on two re-rating catalysts that the consensus is not pricing. The first is the data center CPU opportunity. Qualcomm has been building toward this for years through the Nuvia acquisition and the Oryon CPU core, and the company is now positioned as a credible alternative to the Arm-Intel-AMD triopoly for hyperscaler custom silicon. There is essentially zero data center revenue in the current model and zero data center revenue in the sell-side estimates.

The second and more contentious catalyst is on-device inference. As HBM supply tightness pushes memory prices higher, the economics of running low-complexity, repetitive inference workloads in hyperscale data centers progressively deteriorate. This does not mean that all inference will leave the cloud. Large reasoning, long- context, and agentic workflows will remain in the data center. But workloads where low latency, privacy, and repetitive user interaction matter face a growing economic incentive to migrate to the device. This is also a pattern that has played out repeatedly across compute cycles. Early on, infrastructure and capital concentrate on the server side.

Over time, as costs come down, software matures, and user experience becomes the binding constraint, that compute gradually diffuses toward the consumer edge. From mainframe to personal PC, from server-centric computing to mobile, and now from cloud AI to on-device AI. Qualcomm holds the platform best positioned to capture this transition directly. Its low-power compute footprint — already embedded across smartphones, PCs, automotive, and edge devices — combined with its integrated NPU/CPU/GPU architecture, places it at the center of any redistribution of cloud inference back to the device. We do not know precisely when this shift inflects.

But as memory price inflation and AI usage growth compound simultaneously, on-device inference moves from optionality toward inevitability. And at that point, Qualcomm will no longer trade at today’s valuation. As AI becomes a work platform, inference becomes a recurring production workload. A developer using Claude Code or Codex is running a loop. The same applies for agentic research, legal review, financial analysis, customer support, sales ops, cybersecurity, and eventually – most knowledge work. The question today is: “Who has enough live capacity to serve millions of agents while users are actually trying to get work

” The shortage is not theoretical. From 2023 to 2025, OpenAI’s available compute went from roughly 0.2 GW to 1.9 GW. Revenue moved from $2 billion ARR to more than $20 billion over the same period. More importantly, OpenAI said more compute during that period would have led to faster adoption and monetization, and called compute the scarcest resource in AI. The usage data underneath this is even more important than the headline revenue numbers. By March 2026, OpenAI was generating $2 billion in revenue per month (up to $3 billion as of May). Enterprise had become more than 40% of revenue.

APIs were processing more than 15 billion tokens per minute. Codex had more than 2 million weekly users, up 5x in three months, with usage growing more than 70% month over month. Neoclouds: The Inference Shortage Likewise, Anthropic’s business subscriptions to Claude Code quadrupled from the start of 2026 and enterprise use now represents more than half of Claude Code’s revenue. Anthropic also said customers spending over $1 million annually on Claude doubled from more than 500 to more than 1,000 in less than two months. Anthropic’s run-rate revenue reached $45 billion by May 2026, up 400% from about $9 billion at the end of 2025.

They also admitted that the growth had strained infrastructure and hurt reliability/performance during peak hours. AI labs need usable compute now. Anthropic signed a deal with Amazon for up to 5 GW of compute, including nearly 1 GW by the end of 2026. It signed a deal with Google and Broadcom for multiple gigawatts of TPU capacity coming online starting in 2027 and committed to spending $200 billion on Google Cloud over the next 5 years. Anthropic then announced a SpaceX agreement for more than 300 MW of capacity and over 220,000 Nvidia GPUs within a month.

Anthropic also signed a $1.8 billion, 7-year cloud deal with Akamai for their distributed cloud infra to serve agents at low latency. Once Anthropic got access to SpaceX capacity, it immediately raised Claude Code limits, removed peak-hour reductions for paid users, and increased Claude Opus API limits. More compute means more product availability, more usage, and more monetization. Anthropic is grabbing capacity across every credible route because demand growth is running ahead of infrastructure. If Claude Code, Codex, or a workspace agent is being used inside a real workflow, the customer expects the model to respond immediately.

That forces AI labs to overprovision for peaks, maintain redundancy, and keep spare serving capacity online just like an electricity grid. This is why a shortage shows up as throttled users, lower rate limits, elevated errors, and degraded product experience rather than just “higher compute ” If you are a neocloud with live capacity, then your product is a relief valve in this environment. CoreWeave (CRWV US) reported $66.8 billion of revenue backlog at year-end 2025. They had $60.7 billion of remaining performance obligations, with committed contracts carrying a weighted-average duration of about five years.

By Q1 2026, RPO grew to $99.4 billion, and active power capacity reached 1GW+. They have announced a $21 billion Meta expansion through 2032, a multi-year Anthropic agreement with undisclosed financial terms, and a $6 billion Jane Street AI cloud commitment plus a $1 billion equity investment. Hut 8 (HUT US) just signed a 15- year AI data-center lease in Texas worth $9.8 billion for an initial 352 MW phase. The important details were in the structure: take-or-pay, triple-net, and no early termination. CoreWeave BROADENING DEMAND, STRONG EXECUTION **$99.4B** Revenue Backlog ↑ 284% YOY **$2.1B** Revenue ↑ 112% YOY

**$21M** Adj. Operating Income¹ Active Power Capacity 1GW+ 850MW+ 2022 2023 2024 2025 Q1'2026 49 Active Data Centers 3.5GW+ Total Contracted Power - cohere - Jane Street - Meta - N INTERNAL AS... - ADVAITA - perplexity - ANTHROPIC - WRF - World Labs 1. NON-GAAP FINANCIAL MEASURES. REFER TO THE GAAP TO NON-GAAP RECONCILIATION TABLES IN OUR MAY 7, 2026 PRESS RELEASE. We should not underwrite permanent GPU scarcity. But the explosion in inference demand in the last several quarters, supported by these highly visible deals, suggests that anyone who has available capacity now can re-rate higher – especially names

that we wouldn’t necessarily consider buy-and-hold bluechips. The mad scramble for compute could lead to a more speculative catch-up trade in a wide range of lower-tier operators – including bitcoin mining conversions. Two additional neoclouds that likely will outperform in the wake of the Cerebras IPO due to existing contracts with them are WhiteFiber (WYFI US) and Digi Power X (DGXX US). They’ve begun to take off, but it’s not hard to see how an extremely successful IPO for CBRS can result in a much stronger view being taken on jpeg) Source: Citrini jpeg) Source: Citrini Research

You can view the basket on Citrindex here. In Trade #5 of 26 Trades for 2026, we detailed our view that the AI trade would unavoidably broaden out into the previously-viewed-as-commoditized layer that we dubbed “AI Materials”. We split this into 3 segments – upstream (resins, coatings, polymers, films, powders, chemicals), midstream (laminates, foil, glass cloth, tooling) and downstream (printed circuit boards, IC substrates, system-level assembly). Let’s take a look at how they’ve done. AI Materials Bottlenecks AI Materials Baskets: Performance Since jpeg) Source: Citrini jpeg) All three of these baskets have performed well, following our expectation and historical precedent that the closer they were to the silicon the better they’d do.

A quick recap of how we viewed the status of AI material bottlenecks back in December: Tier 1 was already-running bottlenecks (T-glass, ABF film, CCL, glass cloth), Tier 2 was inflecting (ceramic substrates, HVLP copper foil, low-loss CCL grades), and Tier 3 was the watchlist of materials where demand was inflecting but supply hadn’t visibly tightened. Our top pick for the name with the most exposure to as many potential bottleneck areas was Resonac (4004 JP), and it still remains well positioned to capture further. All of our severe bottlenecks have gotten worse. T-Glass capacity relief has been pushed out from this year to 2027 or further.

Copper foil (HVLP) continues to be a severe bottleneck, massively benefitting the few players capable of production – Mitsui Kinzoku (5706 JP) and Co-Tech (8358 TT) most importantly. Copper-clad laminate lead times have stretched even further, with Korean CCL import prices up 74.5% YoY as of last month, meaning Elite Material Co (2383 TT), ITEQ (6213 TT) are still likely to see earnings higher than estimates for even longer than consensus currently expects. However, in our 26 Trades, we also said we’d continue monitoring areas of emerging interest, as well as ongoing bottlenecks. We believe there are two primary areas in the midstream and downstream that will continue to outperform: PCBs and IC Substrates.

The reasoning is simply that both of these areas need to constantly be upgraded to keep up with the rising complexity necessary to scale AI. Nvidia is marketing the Rubin series as a platform consisting of Vera CPU, Rubin GPU, NVLink 6, ConnectX-9, BlueField-4, Groq LPU, and Spectrum-6. Over the last few generations, accelerator FLOPS have increased by roughly 300x, while interconnect performance has improved by closer to 10x. That gap is becoming the bottleneck. A GPU won’t perform at its max capacity if data, signals, and power don’t move between HBM, CPUs, NICs, DPUs, retimers, switch ASICs, optical modules, power delivery, and eventually other racks at a fast pace.

This is why the PCB (printed circuit board) is being pulled from the background into the center of the AI supply chain. At rack scale, the board becomes part of the high-speed electrical channel. For an accelerator to run at full utilization, the package and board stack have to scale with the silicon. This translates to larger substrates and PCBs with denser build-up layers, finer lines, more microvias, lower-loss materials, smoother copper, better glass cloth, and tighter warpage control. We have spoken about this in Interconnects 101, back in July 2024, but the interesting second order impact that’s happening due to the complexity of Interconnects is the stress on the printed circuit board.

PCBs and the Interconnect Bottleneck As speed rises, the PCB material itself starts affecting performance. If the dielectric loss is too high, the signal attenuates. If copper roughness is too high, conductor loss rises. If the glass weave is uneven, the signal sees different dielectric environments and signal mismatch increases. This is why the PCB requires constant upgrades. The CCL is upgrading from M7 to M8 to M9. The glass cloth is upgraded from Low- Dk to Low-Dk2 to Low-Dk3 or Q-glass. The copper foil in the CCL is upgraded from HVLP3 to HVLP4 to HVLP5.

PCBs are transitioning to higher-layer HDI and selective mSAP/SAP-style fine-line processing and smaller ABF substrates are moving to larger ABF substrates and more SAP-intensive jpeg) Every new AI accelerator asks the substrate to do more. More compute dies, more HBM, more chiplets, more I/O, more power, and more signals moving across a larger package. Nvidia GPU substrate area moved from roughly 3,190 mm² in Hopper to 4,780 mm² in Blackwell, and is expected to reach around 8,000 mm² in Rubin. A bigger substrate takes more panel area, so the same factory produces fewer units. A more complex substrate takes more process steps, so the cycle time gets longer.

A larger body is harder to keep flat, so warpage risk rises. More I/O means more routing, finer lines, more laser vias, more plating, and more SAP capacity. The demand goes up each generation because hyperscalers want more accelerators. The complexity goes up because each accelerator needs a larger, denser, more advanced substrate. The supply is getting squeezed from two sides. The unit demand is rising while the cycle time is also increasing. The same shift is happening at the board level. AI architecture is moving from the server as the basic unit to the rack as the basic unit.

High-speed links increasingly run through switch trays, midplanes, backplanes, NIC and DPU boards, retimer boards, optics boards, and active copper assemblies. This is forcing the material upgrade in PCBs. The shortage in high-end PCBs and substrates is due to a stack of bottlenecks. With every new accelerator generation, AI systems require more board and substrate content: more GPUs, custom ASICs, networking silicon, switch boards, optics, retimers, power boards, and rack-level interconnects. Demand is increasing not only because more AI systems are being built, but also because each system now carries more PCB and substrate content than the last generation.

PCB Fabricators At the same time, each unit is becoming more complex and more time-consuming to manufacture. Substrates are getting larger, PCB layer counts are increasing, tolerances are becoming tighter, and more advanced materials are being used. This means capacity does not scale cleanly with demand. Even if suppliers add capacity, the number of process steps increases, the manufacturing cycles get longer, and the yields go down. This is similar to what happened with HBM. Demand for HBM increased with every accelerator generation, but the product also became harder to manufacture. Each generation brought more dies per stack, more difficult packaging, and longer testing times.

As complexity increased, yields became harder to maintain, especially during the transition from one generation to the next. PCBs and substrates are now going through the same dynamic. Suppliers are being pushed to support new accelerator designs on a 12-15 month cadence, which gives them very little time to climb the yield curve before the next generation arrives. As a result, the yield curve keeps resetting. Demand rises, complexity rises, and usable supply cannot ramp fast enough. That is what creates the structural bottleneck. We have covered the majority of the companies in AI Materials #5 in 26 Trades for 2026, but the companies below have the highest upside in our opinion.

IC Substrates Our top single pick for continued outperformance in AI Materials is Ibiden (4062 JP). At the accelerator package level, the bottleneck begins at the IC substrate. AI GPUs and custom ASICs are getting physically larger because they need to connect more compute dies (2 dies or 4 dies), HBM stacks (6 to 8 to 12 stacks), chiplets, I/O dies, power-delivery structures, and the server board. As package size grows, each substrate consumes more ABF material, copper, T-glass, plating chemistry, and panel area. A production panel that previously yielded many smaller substrates now yields fewer large AI substrates.

Even if factory capacity is unchanged, effective unit output falls. Back in December, we highlighted the parabolic rise in Tungsten as an area to monitor for emerging bottlenecks in 2026. Tungsten Hexafluoride (WF6) is used in tungsten CVD for via fill and contact metallization at advanced nodes, and demand intensity scales directly with HBM stack height and 3D NAND layer count. Supply is concentrated across Kanto Denka, SK Materials (held by SK Inc, 034730 KS), Merck KGaA (Formerly Versum), and Air Liquide, with the China localization push absorbing a meaningful share of domestic capacity. Contract pricing has been ratcheting higher for six straight quarters and the latest signals suggest the curve is steepening, not flattening, as we approach the HBM4 capacity ramp.

Following supply chain disruptions due to the conflict in Iran, we’re confident that we’ll see this bottleneck become even more pronounced than it already is. Emerging Upstream Bottleneck: Specialty Gases (WF6) Kanto Denka (4047 JP) is the cleanest pure-play. Fluorine chemicals run roughly 35% of revenue but a much larger share of segment EBIT, and inside that segment the WF6 and electronics gas business is the growth engine. When we wrote about the coming ascendancy of the Korean stock market in August 2025’s State of the Themes, there were limited ways that an international individual investor could express the trade – we contented ourselves with EWY.

But now, Korean equities are available broadly. As we move forward, our Korea Semis analyst Jukan will be more freely examining Korean stocks (especially because we won’t have to deal with hundreds of people complaining they can’t invest in them). Within the bottleneck-hunting game, there is one area that is both the most obvious and still meaningfully under-discounted in the price — leading-edge foundry. AI accelerators, custom ASICs, HBM base dies, networking chips, CPUs, XPUs — all of them ultimately come off a leading-edge logic wafer. HBM, CoWoS, optics, and substrates have all become critical bottlenecks, but the starting point of every one of these bottlenecks is still leading-edge process capacity.

Korea Unlocked TSMC has already signaled that AI demand is exceptionally strong and that supply constraints persist on both leading-edge nodes and advanced packaging. “Thus, we are using multiple levers to do everything we can, wherever we can, however we can to maximize the support to all our customers across all platforms. The demand are [sic] very robust, especially from the HPC and AI applications. And also, we try very hard to speed it up and pull in all the equipment as we can. Still our supply is very tight. Demand continues to ” -

C. Wei, Q1 2026 Earnings Call This is where the bull case on Samsung Foundry (005930 KS) begins. The Samsung Foundry thesis isn’t that Samsung beats TSMC over a short horizon but that Samsung Foundry can be re-rated as the most realistic second source of leading- edge capacity. Intel Foundry’s existence cannot be ignored, of course. Intel holds powerful strategic assets — leading-edge manufacturing presence on US soil, advanced packaging, the x86 ecosystem, and government backing. From a geopolitical standpoint, Intel could become an extremely important player over the long run. For US customers in particular, the strategic value of having a “domestic leading-edge foundry” option is undeniable.

But what customers want right now is not a long-term vision — it is an executable alternative that can actually tape out a product on time and carry it through to volume production. By that yardstick, Samsung is a more meaningful present-tense player than Intel. Samsung already has leading-edge foundry production experience, has been running real customer products on 4nm/3nm, and possesses a vertically integrated structure spanning memory, logic, and packaging. Intel Foundry, by contrast, still has to clear hurdles around expanding its external customer base, validating process reliability, and securing high-volume production references with marquee customers.

In short, Intel looks more like a long-dated call option on a US-centric foundry, while Samsung looks like the more realistic global second source capable of absorbing TSMC’s bottleneck today. The moment the market begins to acknowledge this possibility, Samsung Foundry stops being viewed as a structurally broken business unit and starts being repriced as a scarce option within the AI infrastructure supply chain. Per our industry checks, there is a meaningful probability that Samsung Foundry is involved in portions of the memory-adjacent custom silicon program tied to Marvell’s recently rumored Google hyperscaler AI infrastructure work.

Why does this project matter for Samsung Foundry? As hyperscalers continue to expand the custom logic, memory expansion, CXL, and inference acceleration chips that surround the TPU, the number of programs competing for TSMC’s leading-edge capacity keeps rising. In that environment, Samsung does not need to displace TSMC on flagship accelerators. It only needs to recover enough trust to absorb a portion of the AI/HPC peripheral logic, memory-adjacent ASICs, and second-source programs where schedule reliability and supply-chain diversification matter most. So who stands to benefit from this project? Doosan Tesna is Korea’s #1 system semiconductor wafer test OSAT, with the overwhelming majority of its revenue tied to 12-inch system semiconductor testing for Samsung Foundry.

As the de facto default vendor for back-end testing of system semiconductors coming out of Samsung Foundry — Exynos, CIS, AP, MCU — Doosan Tesna’s volumes scale directly with Samsung Foundry’s utilization rate. Why now? Because the company is already moving. In October 2025, Doosan Tesna disclosed the acquisition of testing equipment worth KRW 171.4 billion. The stated rationale is Apple CIS. Samsung has broken into the Apple CIS supply chain that Sony had effectively monopolized, and the structure that has now settled in is straightforward — Samsung’s Austin fab handles front-end wafers, Doosan Tesna handles wafer test, and Samsung handles packaging.

The line goes live in 2H26. Doosan Tesna (131970 KS) Mobile CIS is cyclical, but given the nature of Apple as a customer, lines that get qualified-in tend not to come out. This is a line that pulls Doosan Tesna’s revenue base up a notch. The problem is that the KRW 171.4 billion was just the start. On April 28, 2026, Doosan Tesna filed two separate disclosures. The first was a KRW 190.9 billion acquisition of Teradyne and Semes equipment. Teradyne ATE is for SoC testing, not memory. The destination, per our checks, is Nvidia’s LPU.

The chip leverages the inference acceleration tech Nvidia absorbed through its Groq “acquisition”, with production nodes running on Samsung Foundry through the LP30/LP35 generations. Equipment installation wraps up by October 30, 2026, with meaningful revenue contribution kicking in from 4Q26. Applying the rule-of-thumb conversion rate the OSAT industry typically uses (~30% of capex translating to revenue) gets you to roughly KRW 50–60 billion of incremental annual revenue ($30–$40 million). The number itself isn’t trivial, but what matters more is the nature of the customer. Until now, the market has bucketed Doosan Tesna as a Samsung Foundry-tied mobile AP/CIS testing house.

The KRW 190.9 billion disclosure is the first crack in that frame. It’s the moment a global tier-1 AI accelerator OEM enters Doosan Tesna’s customer base directly — the moment its revenue mix starts shifting from a mobile cycle to an AI infrastructure cycle. That said, the LPU bet has an expiration date. From the LP40 generation, Nvidia looks set to move production to TSMC. The revenue window the KRW 190.9 billion creates is powerful, but it isn’t sticky. This is where Marvell’s Google-bound memory-adjacent custom silicon — discussed earlier in this note — re-enters the picture.

Marvell is a different animal from LPU. Set to be produced on Samsung’s 4nm and slated to launch in mid-2027, this chip has a meaningful probability of migrating onto Samsung Foundry’s 2nm in the next generation. That isn’t a single-node window — it’s a sticky workload that follows the node migration cycle. Marvell matters for Doosan Tesna not because it’s “another large customer,” but because it’s the most plausible candidate to backfill the seat that LPU vacates. The company is already looking at this picture. The second disclosure on April 28 — the amendment to the Pyeongtaek Plant 2 capex disclosure — is the evidence.

The investment amount was revised up from KRW 220.6 billion to KRW 230.3 billion, and the completion deadline was pushed from March 2027 to November 2027. Two points matter here. First, the construction that had been paused on softer 2025 demand has been resumed. Second, the project is being run on a Shell First framework — putting up the building and clean room ahead of demand, with equipment capex deployed in stages as demand materializes. Shell First is the conservative skeleton OSAT players lay down when they have visibility on demand they’re confident in. Restarting a paused project means the picture the company is now seeing for post-2028 back-end testing demand has shifted versus how it looked in 2025.

And the November 2027 completion timing — landing just months after Marvell’s mid-2027 launch, and overlapping with LP40’s transition to TSMC — is what gives this disclosure its real meaning. The shell goes up in time to catch Marvell’s ramp from day one and to receive whatever fills the void LPU leaves behind. KRW 171.4 billion is Apple CIS coming online from 2H26 — base load. KRW 190.9 billion is LPU ramping hard from 4Q26 and tapering into LP40 — a short-cycle boost. Pyeongtaek Plant 2 is the long-cycle skeleton — sized to capture Marvell’s ramp from its mid-2027 launch and to receive other 2nm ASICs into the seat LPU leaves behind.

These are three stages of the same picture. Doosan Tesna captures the back-end side of Samsung Foundry’s recovery. But the foundry recovery does not start at wafer test. It starts earlier, at tool move-in. Before Doosan Tesna tests Apple CIS, LPU, Marvell, or future 2nm ASICs, Samsung first has to install the front-end tools that make those wafers possible. That is where Wonik IPS enters the series. This section benefited from research input and industry context from Damnag. com/@damnang Our second pick in the Samsung Foundry Beneficiary Series is Wonik IPS. Wonik IPS (240810 KS)

If Doosan Tesna is the back-end testing beneficiary of Samsung Foundry’s utilization recovery, Wonik IPS is the front-end equipment beneficiary of Samsung Foundry’s capacity build-out. Doosan Tesna gets paid when wafers start flowing. Wonik IPS gets paid before that happens. Before Tesla, Marvell, or any other 2nm ASIC customer can enter volume production, Samsung first has to fill Taylor with tools. EUV, etch, deposition, and metrology equipment go in before customer revenue appears. That timing difference is the core of the Wonik IPS thesis. Wonik IPS matters because Samsung Foundry’s leading-edge expansion is both a lithography and deposition story.

Samsung’s 3nm GAA mass production already used a new PECVD process based on Wonik IPS’s GEMINI platform. EUV-compatible novel films, SADP films, and low- temperature hard-mask quality control were part of the process stack where Wonik IPS was cited. As Samsung moves from 3nm GAA to 2nm and expands Taylor around advanced logic customers, the process complexity does not fall. It rises. More GAA integration, more EUV-linked film requirements, more hard-mask control, and more multi-patterning complexity all increase the value of qualified deposition vendors already inside Samsung’s advanced node ecosystem. The relationship with Samsung runs deep.

Samsung Electronics and Samsung Display each hold a 3.77% stake in Wonik IPS. Over 50% of total revenue is attributed to Samsung Electronics. Wonik IPS moves first when Samsung invests and goes quiet when Samsung pauses. The upside comes from this, and so does the risk. The reason to revisit Wonik IPS now is Taylor 1 becoming real, and Taylor 2 moving from a long-term option into an active review tied to 2nm customer discussions. For a long time, Taylor was a fab without a customer. Samsung could build the shell, but without an anchor customer, equipment deliveries could be delayed.

That was the problem. Tesla changed Taylor 1. The $16.5 billion long-term supply agreement turned Taylor from an empty strategic asset into a fab with an anchor workload. Samsung now expects Tesla-related chip production to begin in 2H27, with the fab entering its operational launch phase in 2026. Taylor 2 is the next layer. Samsung has now begun an early review of a second Taylor fab, with the review being conducted in parallel with global customer order discussions for advanced 2nm logic. That matters because a second Taylor fab would not be a memory fab.

It would be another leading-edge logic capacity addition. And leading-edge logic capacity additions are exactly where deposition intensity rises. Memory is not the core reason to own Wonik IPS, but it adds a second layer of upside. The foundry thesis alone is enough to put Wonik IPS on the map. But the setup is stronger because the company is not a pure foundry supplier. It also has exposure to Samsung Memory and SK hynix capex. If HBM-driven wafer allocation tightens conventional DRAM supply and forces another memory investment cycle through P4, P5, M15X, and Yongin, Wonik IPS gets a second lever.

Samsung Electro-Mechanics (009150 KS) If the Samsung Foundry thesis can be summarized in one line as “the most realistic call option on TSMC overflow,” then Samsung Electro-Mechanics is the lowest- strike option on that trade. Every time Samsung Foundry wins a new AI/HPC program, the chip must pass through two stages before it can ship — FC-BGA substrate and MLCC — and Samsung Electro-Mechanics holds first-tier vendor status in both. Once a leading-edge logic wafer leaves the fab, the next bottlenecks are, first, advanced packaging, and second, substrate (although the first is moot here, since most chips currently produced on Samsung Foundry’s leading-edge nodes do not use AVP).

AI accelerators, custom ASICs, HBM base dies, networking chips — all of them must ultimately sit on a high layer-count FC-BGA. Global FC-BGA capacity has already begun to tighten. Major suppliers — Ibiden, Unimicron, Nan Ya PCB, AT&S — are all prioritizing allocation toward AI substrates, and the ramp-up timeline for currently announced CAPEX is, at the earliest, mid-to-late 2027. Within this structure, Samsung Electro-Mechanics’ position is not merely that of a global top-tier supplier, but rather the de facto captive first-tier substrate vendor for any chip taped out at Samsung Foundry. In other words: ● If the scenario in which Samsung Foundry participates in MRVL’s Google hyperscaler memory-adjacent ASIC program materializes, the primary FC-BGA order for that chip is most likely to flow to Samsung Electro-Mechanics.

● Every time Samsung Foundry secures additional external customer wins on 4nm/3nm/2nm GAA, new SKUs accumulate within the Samsung Electro-Mechanics FC-BGA mix. Put differently, the further Samsung Foundry normalizes, the more FC-BGA references Samsung Electro-Mechanics accumulates, laying the groundwork to penetrate the high-end segment that has so far been blocked off by the incumbents (Ibiden, Unimicron). Our preference for Samsung Electro-Mechanics is not driven solely by the Samsung Foundry normalization theme. If anything, we believe the MLCC shortage cycle will have a larger impact on forward earnings. The MLCC shortage cycle is a variable entirely independent of the Samsung Foundry thesis.

But the fact that both variables converge on the same name is precisely what makes the risk/reward on Samsung Electro-Mechanics asymmetric. MLCC content per AI server is increasing exponentially. Industry checks indicate that MLCC content per Rubin Ultra system is roughly 1.8 million units, approximately 90x the level of H100. MLCC lead times have already extended to 24 weeks — about 3x the actual production cycle of 6–8 weeks. This points to a tight supply environment in which strong downstream demand leaves little room to build inventory. That said, the more important point in the Samsung Electro-Mechanics bull thesis goes one step further.

Specifically, if AI server power delivery transitions from 48V to 800V DC, an entirely new demand layer for ultra-high-voltage MLCCs is added on top. Under the current 48V power architecture, MLCC demand can be broken into two broad buckets. The first is MLCCs used in power conversion and voltage stabilization. The second is MLCCs used around the major silicon — GPUs, ASICs, CPUs — for decoupling and noise suppression. The shortage that the market is currently focused on is largely concentrated in the latter bucket: high-reliability MLCCs supporting high-performance silicon. The story changes once power delivery transitions to 800V DC.

A portion of the MLCCs that previously played the voltage stabilization role under 48V architecture will need to be replaced by ultra-high-voltage MLCCs capable of handling far higher voltages. In other words, the shift in AI server power architecture does not simply increase MLCC demand around the silicon — it creates additional high-voltage MLCC demand at the power conversion stage as well. This matters because 1,000V-class ultra-high-voltage MLCCs are meaningfully more expensive than standard 100V-class MLCCs. On a retail price basis, the cost gap is estimated to be greater than 10x. For Samsung Electro-Mechanics, this is a highly significant structural shift.

The company is already one of the major high-end MLCC suppliers globally alongside Murata, TDK, and Taiyo Yuden, with particular strength in high-reliability MLCCs for IT, automotive, and industrial applications. As a result, the expansion of demand for high-reliability and high-voltage MLCCs into AI servers feeds directly into Samsung Electro-Mechanics’ ASP and margin structure. In particular, once the MLCC shortage — which began in high-reliability server- grade products — forces suppliers to reallocate capacity toward AI servers, the supply tightness is likely to spill over into adjacent end markets: mobile, automotive, and industrial. This is the same pattern we have already observed in both the memory and glass fiber cycles.

For Samsung Electro-Mechanics, this generates two distinct effects: first, an increase in revenue from high-end AI server-grade MLCCs; and second, improved pricing power across the entire MLCC portfolio. We close out the Korea Unlocked series with LG Innotek. While LG Innotek’s direct exposure to Samsung Foundry is limited, the name most compactly captures the structural reconfiguration unfolding across Korea’s tech supply chain. LG Innotek (011070 KS) SiP Substrates: A Bottleneck Manufactured by Supplier Exit Every major substrate player globally is retooling capacity toward server- and AI- grade FC-BGA. What the market has yet to price in is the second-order consequence: as the entire industry migrates to FC-BGA, SiP substrates for smartphones, wearables, TWS, and AR/VR devices are entering structural undersupply.

Without the alphabet soup - big players chase high margin shiny object with all their resources, stop making lower margin older stuff, supply of older stuff (even though it’s not seeing AI level demand) contracts, any sort of new demand or even just existing demand must be fulfilled, older stuff becomes higher margin for the few players left making it. This is the same playbook we’ve already seen in DRAM and T-Glass. In the Macronix case, the major NAND vendors concentrated on eSSD, TLC, and QLC while exiting legacy eMMC, SLC, and MLC NAND, leaving Macronix — the legacy NAND specialist — in de facto command of that market.

In the Nanya Technology case, the DRAM Big 3 redirected capacity into DDR5, creating a DDR4 shortage severe enough that NAND makers took equity stakes in Nanya. The point is not that SiP TAM is growing at AI-like rates. On demand growth alone, this thesis looks thin. But when suppliers are actively exiting the category, modest demand growth is more than enough for survivor economics to play out. Currently, margins are projected to stay low for LG Innotek - around 9-9.5%. If we see the same kind of squeeze play out here as we did in MLC NAND, we think LG Innotek could see 2028 gross margins as high as 14% - currently expected to be 9.5%.

This is our third Semis Memo since we began the series on the thesis that the AI- related semiconductor industry would begin dominating the narrative. Updating Previous Semi Memo Ideas We are always on the lookout for the next big sub-theme for the AI infrastructure trade. We’ve done this since we first began our coverage of it with Artificial Intelligence: Global Equity Beneficiaries. However, we’ve picked up a lot of new readers since then, so we figured it is a good time to remind everyone of something: just because we’re on the lookout doesn’t mean that anything is wrong with what we’ve already covered.

Just like you could have bought the names we listed in our May 2023 AI primer and never bothered to figure out another bottleneck again (and roughly 6x’d from that), we want to make it clear that it’s our job to sniff out the next mispricing. Nothing about that means that the previous mispricings have fully resolved. As our current dynamic AI allocation shows, we’re still quite bullish on many of the ideas we’ve covered YTD. So let’s look at how our previous collection of ideas from our first two Semis Memos have done – of course, you could have pretty much put all of SOXX on a dartboard, thrown a dart and pulled a pretty solid return buying whatever it landed on.

This is less of a victory lap (not that we are averse to victory lapping, it’s just in bad taste when it’s this straightforward) and more focused on presenting what’s performed better in relative terms to highlight where the opportunities still are. Our January Memo was titled “Muscle Memory” and examined the best second order beneficiaries of the Memory Supercycle. Namely, these were Memory Testing, Semicap Subsystems and the Legacy Memory Squeeze. Our Memory Testing was led by Aehr Test Systems (AEHR US). And despite being up more than 300% since when we bought, we’re staying long.

In fact, we’re adding. AEHR reported their lead hyperscale AI customer (GOOG) placed a $41 million follow-on production order for package-level burn-in of custom ASICs (TPUs), with deliveries starting in fiscal 2027. That puts second-half bookings above $92 million with six weeks still left in the quarter against a roughly $3.2 billion market cap that the sell-side is still modeling off FY26 print. But that’s not the point, the order book has already pulled into FY27, which is the period the street will be forced to re-cut models around once the next two quarters of shipments and follow-on awards actually land.

AEHR’s FY27 revenue conversion turns them into a scarce piece of AI infrastructure with reorder cadence, installed-base consumables, second-customer optionality, and pricing power that scales with ASIC complexity. As custom ASICs get hotter and more mission-critical, early-life failures become an uptime liability sitting inside a training cluster that costs a LOT of money to run by the hour. Consistent with our entire memory testing thesis, burn-in turns into a cheap insurance policy on very expensive silicon. AEHR is being designed at both the package level (Sonoma) and the wafer level (FOX), and management has now pointed at silicon photonics.

And the name still has SiC, GaN, flash, and HBM as the next demand vectors. The customer-concentration argument that worked twelve months ago gets harder to defend every quarter. The recent $60 million ATM was dilutive in the most literal sense, but it cleared the balance-sheet question right as order flow is accelerating, which is unusual timing for one of these raises and a useful tell on management’s read of demand. Put it all together and the asymmetry is clean. The discovery move has already happened. There is further re-rating yet to occur on their TPU socket and potential further custom ASIC wins from other hyperscalers.

We believe we can see AEHR double still despite the massive run up. We’re also aware that it’s likely to trade with significant volatility given crowding, so rather than increasing here we’ll be waiting to be a buyer on dips to increase our position. Our second semis memo, “Let There Be Light”, focused on the photonics supply chain. It has performed even more impressively, up more than 75% in just two months, while our single stock highlight Himax (HIMX US) soared +125% as earnings validated our thesis on their COUPE upside being significantly mispriced. We remain bullish on Himax as well.

Just as we’ve done, we’ll continue to update our active AI allocation opportunistically to some of our new picks and manage risk on our old ones. It should go without saying, but I’ll still say it, that the move in semis over the past 6 weeks has been extremely violent and - even in a raging bull market - it’s likely for there to be pullbacks that provide better entry points on single stocks. We are guilty of the very same ADHD focusing on the next thing as we have cautioned you against in the last section.

While we were some of the earliest to look past the dismal environment for memory coming out of 2023 and emphasize the asymmetric HBM setup in memory OEMs back in January 2024, we also sold them too soon (in February 2026, right before they went parabolic). Some Thoughts on Where Weʼre Headed It has been somewhat difficult to balance, over the past 3 years (literally, May 29, 2026 will mark the 3 year anniversary of our first AI primer on the coming data center scale up that would 10x analyst estimates). Every time we think we’re too bullish on AI, something surprises us more.

Back in 2024, we wrote as part of our January State of the Themes: “UBS is predicting AI industry revenue to grow to $420 billion by 2027, a 40% increase from its prior view of $300 billion. This would represent a 72% CAGR from $28 billion in 2022. And that’s conservative, by “bubble” standards. These are still easily achievable goals. If we are actually going into an AI bubble, it can get so much crazier. Looking at the telecom bubble of the early 2000s for a parallel, they were modeling all humans on earth with 2 cell phones.

They modeled people in 2000 going from spending 15% of disposable income on internet access to 60%. It is the base case that AI will be the size of the entire current global semiconductors market and 4x the annual capex of all the hyperscalers. This means there is still much room for estimates to get wildly out of hand in a bubble- like ” Our view, back then, was that total AI spend would be five times higher than UBS’ estimate – the highest on the street at the time. And still, we were too conservative.

It’s now estimated that in 2027 AI spending will be in excess of $3 trillion. What will someone laugh at today that will be true 24 months from now? That’s the question that’s been on the more bullish side of my thoughts. Back then, it was primarily just me writing these newsletters and I had to try my best to temper my most bullish expectations because my job was to convince people – and we were still in a place where wild optimism got dismissed easily. I have always tried to balance a realistic outlook that takes into account the near certainty that estimates

would get too insane, markets would overshoot to the upside and we’d blow and then burst a bubble with the deep conviction that AI is the most important investment theme of our lives. I think I’ve done a good job of that, but it has undoubtedly begun to be a hindrance. Every cycle convinces the most rational of investors to become comfortable with expectations that are impossible. That’s what the more paranoid side of my brain says. So let’s address what can happen from here… On one side, there’s the argument that we’ve entered a bubble.

I think this is primarily driven by perceptions around the speed at which memory stocks have moved and the crowding in of capital that has made AI really the only thing that seems worth investing in. I am certain without a doubt that markets will get ahead of themselves and begin pricing in things that won’t happen. Are we there yet, though? If one just looks at the rally in KOSPI - the forward PE multiple has gone DOWN since this rally began. We have gone from “memory is in a structural glut” to “memory isn’t cyclical anymore” in the span of just more than two years.

We still believe that memory, like all semiconductors, remains cyclical, despite AI. But the shape and duration of that cycle is highly dependent on the persisting bifurcation between HBM and commodity DRAM, and whether NAND follows a similar supply tightness from AI demand. On the other side, there’s the leagues of serious experts talking about how insane the demand is. They’re all much smarter than I am. The claim made here is that by the early 2030s, global AI inference could be 10,000x larger, driven by 50x algorithmic progress, 50x hardware and systems progress, and 4x data center capacity…

Agentic AI demand scenarios imply a multi-year supply bottleneck. Old chatbot-anchored assumptions vs new agentic-anchored assumptions. md) At roughly 47M H100-equivalents of demand, several chokepoints bind. jpeg) In the base case, demand reaches roughly 47M H100-equivalents by 2030, while key supply chokepoints sit far below that level. If this base case is right, demand likely outruns supply for **more than 5 years**. Source: CRA-I expectations summary. Design: Citrini Research. Citrini Research If expectations like this become the consensus, then yes, it's not difficult to envision a scenario where analysts can easily justify SNDK or MU or SK Hynix tripling from

here. And maybe Sandisk does continue to see datacenter mix shift, we normalize peak earnings, value it at a 5% FCF yield, and it trades multiples higher from here. Or, HBM demand continues to voraciously consume any and all incremental capacity out to 2029, putting SK Hynix at 2x 2029E EPS. These outcomes are entirely possible because they’re much more a function of imagination about the future than discounting an extrapolation of the present. That imagination has repeatedly proven to be too conservative in its optimism. But as significant as this all is, I think it’s worthwhile to reserve a small part of your brain to remember to be on the lookout for the signs.

I’m not too concerned about whether or not we are entering a bubble, because every bubble that’s burst in the past 50 years has happened following the Fed tightening monetary conditions. Right now, the economy is great and the Fed is on hold. It’s not going to be the technology that causes this to stop because we can keep scaling it and keep spending and keep coming up with new Jevons-y reasons why we will never have enough compute. Like always, it will be macro. So, as uninspiring as this is, my strategy remains the same as always – play the game, remain on the side of the technology, don’t anesthetize myself with unrealized gains to the point where I ignore the indications that have consistently signaled the top dozens of times before or buy in to the idea that cycles don’t exist anymore.

Keep updating the potential list of scenarios we can encounter that pose risks to ever increasing estimates and maintain a robust set of signals that indicate we’re going down one path or another. This article is for informational purposes only and does not constitute investment advice. By accessing this material, you agree to our Terms of Service.